1. Field of the Invention
The present invention generally relates to switched-capacitor circuit, and more particularly to a switched-capacitor circuit which is used in a pipelined analog-to-digital converter (ADC).
2. Description of Related Art
The growing demands for portable communication and audio/video electronic devices call for longer operating time. The battery power, however, could not keep up with pressing need of longer operating time. Reducing power consumption is thus becoming an alternative and more feasible way to reach that object.
The pipelined analog-to-digital converter (ADC) is widely utilized, over other ADC architectures. FIG. 1 illustrates a conventional pipelined ADC architecture 1. The input signal Vin is firstly sampled by a front-end sample-and-hold amplifier (SHA) 11, which then provides a stably held signal to a later stage 12. As shown in the expanded block, each stage 12 includes a sub-ADC 121, a sub-DAC (digital-to-analog converter) 122, a sample-and-hold amplifier (SHA) 123, an analog subtractor 124 and an amplifier (Gi) 125. In the design of high-resolution pipelined ADC 1, a high-gain op-amp is usually used to process analog signal with high accuracy. However, in advanced CMOS process, the gain value of the amplifier (Gi) 125 will be getting smaller due to the facts that the intrinsic gain of the transistors may decrease and the power supply of the pipelined ADC architecture 1 will decrease. Therefore, the high-gain op-amp will face serious design challenge in switched-capacitor circuits.
In order to correct the gain-error of a low-gain op-amp, a correlated double sampling ADC is provided recently, which uses two pairs of capacitors to sample and control the two pairs of capacitors to perform amplifying in different time. This technique nevertheless requires an additional pair of capacitors (or more silicon area), two pairs of capacitors causes double loading, which results in more power consumption. Furthermore, three clock phases are needed in this technique, and thus reduce the operating speed of overall circuits.
For the reason that above-mentioned conventional ADC architectures have respective disadvantages, a need has arisen to propose a novel switched-capacitor circuit which can correct gain-error while using low-gain op-amplifiers to improve the overall efficiency of conventional pipelined ADC architectures.